Adaptive Hybrid Radix-2^k FFT Processor Architecture
A hardware architecture for large-size FFTs that adaptively fuses the two classical FFT processor styles - pipelined (high throughput, low utilization) and memory-based (compact, low throughput). It builds radix-2^k multi-path delay commutator (MDC) units for large transforms, a conflict-free memory access scheme that avoids bank contention, and a proven family of bit-dimension permutations for input reordering that satisfy variable-length, high-radix, and arbitrary-parallelism constraints. On FPGA it uses fewer computation cycles than memory-based designs and higher hardware utilization than pipelined ones.
Adaptive Hybrid FFT: A Novel Pipeline and Memory-Based Architecture for Radix-2k FFT in Large Size
Proposes a hardware architecture for computing large fast Fourier transforms that adaptively blends the two classical FFT processor styles: pipelined designs (high throughput, poor hardware utilizati…