Direct Memory Access and Cache Coherency
Direct memory access lets a device read and write main memory by itself, so the processor is free while a large transfer happens. The catch is that the processor keeps recent memory in fast caches, so the device may write bytes the processor never notices, or read stale bytes the processor has not written back yet. A driver therefore has to use memory the system keeps consistent, or explicitly hand ownership of a buffer back and forth, and skipping that gives you a transfer that looks fine but delivers old or garbage data intermittently.
Questions this Concept answers
- Why can a device read stale bytes from a buffer the driver just filled, even though the driver's own reads of that buffer look right?
The Linux DMA API: Coherent and Streaming Mappings Explained
This article explains how a Linux driver lets a device read and write main memory safely. The core problem is that the address a device uses is not the address the processor uses, and on many machine…