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FPGA Inference Acceleration of Gradient-Boosted Decision Trees with Lookup Tables

A hardware design method (TreeLUT) that maps a trained gradient-boosted decision-tree ensemble entirely onto FPGA lookup tables, using a tailored fixed-point quantization scheme and pipelining so inference needs only comparisons and additions, achieving ultra-low area and latency without block RAM or DSP blocks.

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TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient

TreeLUT is an open-source tool and hardware architecture for implementing gradient-boosted decision tree (GBDT) classifiers directly on FPGAs to accelerate machine-learning inference. Because a decis…