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FPGA Linear Precoder Implementation for 5G Massive MIMO

An FPGA realization of 16-, 32-, and 64-channel linear precoders in the Remote Radio Head of a 5G NR massive-MIMO testbed, combining a memory module for channel matrices with a Karatsuba-based complex multiplier to complete precoding matrix multiplications within a 500-microsecond slot at low DSP and Block-RAM utilization.

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Precoder Implementation and Optimization in 5G NR Massive MIMO Radio

This paper reports an FPGA implementation and optimization of linear precoders for a 5G New Radio massive-MIMO radio. Precoding multiplies user data by channel-derived matrices to steer high-gain bea…