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Johnny Five
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FPGA Soft-Core DAQ Firmware for Resistive Plate Chamber Readout
An interrupt-driven data-acquisition design in which a NIOS II soft-core processor instantiated inside an Intel Cyclone IV FPGA turns each Resistive Plate Chamber front-end into a self-contained, network-enabled readout unit (RPC-DAQ). On a global trigger an event interrupt service routine reads XY strip and timing data from the FPGA logic, frames a timestamped event packet into a FIFO, and hands it to an embedded Ethernet controller for background TCP/UDP transfer to back-end concentrators. Separate timer-driven routines perform periodic health monitoring, high-voltage control, command handling, and remote firmware upgrade. The soft-core approach trades FPGA logic and block RAM for customizable word length, clock, memory, and peripherals, and the architecture is designed to scale to the 28,800 RPC-DAQ units of the INO-ICAL neutrino experiment.