Conceptual

GRAMC: A Reconfigurable In-Memory Analog Matrix Computing Architecture

In-memory analog matrix computing with resistive memory solves a matrix problem in one settling step, but every published circuit wires its array to its amplifiers in one fixed way and therefore computes one fixed function. GRAMC makes the wiring itself programmable: register-controlled transmission gates reconfigure a 128x128 1T1R array and its operational amplifiers to perform matrix-vector multiplication, inversion, pseudoinverse or eigenvector extraction. Around that macro sits an on-chip write-verify loop for 4-bit multi-level programming and a digital control module for the nonlinear operations, yielding a hybrid analog-digital solver that runs both matrix equations and LeNet-5 inference on MNIST.