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High-Level Synthesis for FPGA Hardware Acceleration in High-Energy Physics

How High-Level Synthesis (HLS) lets physicists implement software algorithms on FPGAs by writing them in C or C++ and synthesizing them into hardware, instead of hand-coding hardware description languages. The student learns the HLS design flow, the parallelism, pipelining, and memory-optimization techniques that turn a track-finding algorithm into a low-latency firmware module, and how such accelerators serve real-time triggering in collider experiments.

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Harnessing Hardware Acceleration in High-Energy Physics through High-Level Synthesis Techniques

A tutorial on High-Level Synthesis (HLS), a design methodology that compiles algorithms written in C or C++ into hardware description languages for implementation on FPGAs, applied to real-time data …