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High-Temperature Delta-Sigma ADC in Standard SOI CMOS to 250 Celsius
A second-order discrete-time delta-sigma analog-to-digital converter, fabricated in an automotive-grade 0.18um SOI CMOS process, engineered to operate reliably at 250C, far beyond the process's 175C qualification. Dedicated design techniques (dummy-transistor leakage compensation, clock-boosting to limit pass-gate cross-talk, and stability-oriented architecture) sustain 12 effective bits and >93 dB SNR at high temperature with only 13.7% area overhead.