About Lecture -1 Introduction to Computer Architecture

Recursion and Activation Records Multi-Cycle Processor Design Procedure Calls and Calling Conventions Binary Division Algorithms Processor Exception Handling Handling Pipeline Control Hazards Datapath and Control Unit Design Booth's Algorithm for Signed Multiplication Finite State Machine Processor Control Critical Path Delay Analysis for Carry Skip, Carry Select, and Ripple Carry Adders Microprogrammed Control Single-Cycle Processor Design Pipelining & Hazards IEEE 754 Floating-Point Arithmetic Memory Hierarchy and Locality of Reference MIPS Control Flow Instructions PLA-Based Control Unit Synthesis Virtual Memory and Page Tables Instruction Encoding Formats Benchmarking Processor Performance The CPU Performance Equation Bus Arbitration and Master/Slave Protocols Cache Organization and Mapping Strategies Resolving Pipeline Data Hazards RISC versus CISC Architectures Instruction Set Architecture Design Trade-offs ALU Design and Binary Arithmetic Multilevel Page Tables and the Translation Lookaside Buffer Overflow Detection in Arithmetic Logic Units Polling, Interrupts, and Direct Memory Access Direct-Mapped versus Set-Associative Caches Input/Output Buses and Interfaces Pipelined Processor Datapath Design The Five Generations of Computers